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AlienVault OTX
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blackfive@fakenhamweb.co.uk
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NS2.SIMPLEREG.COM
Created
2012-04-13 00:00:00
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2016-04-07 00:00:00
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2018-04-13 00:00:00
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page-item-945>a hrefhttp://retroramblings.net/?page_id945>Links and Resources/a>/li>/ul>/li>li classpage_item page-item-1377 page_item_has_children>a hrefhttp://retroramblings.net/?page_id1377>Turbo Chameleon 64/a>ul classchildren> li classpage_item page-item-1380>a hrefhttp://retroramblings.net/?page_id1380>Arcade Cores/a>/li> li classpage_item page-item-1894 page_item_has_children>a hrefhttp://retroramblings.net/?page_id1894>Computer cores/a> ul classchildren> li classpage_item page-item-1859>a hrefhttp://retroramblings.net/?page_id1859>Amstrad CPC464/6128 for Turbo Chameleon 64/a>/li> li classpage_item page-item-1984>a hrefhttp://retroramblings.net/?page_id1984>Archimedes core for Turbo Chameleon 64/a>/li> li classpage_item page-item-1705>a hrefhttp://retroramblings.net/?page_id1705>Atari ST (MiSTery)/a>/li> li classpage_item page-item-1841>a hrefhttp://retroramblings.net/?page_id1841>BBC Micro/a>/li> li classpage_item page-item-1612>a hrefhttp://retroramblings.net/?page_id1612>Commodore 16 / Plus 4/a>/li> li classpage_item page-item-1989>a hrefhttp://retroramblings.net/?page_id1989>IBM PC/XT core for Turbo Chameleon 64/a>/li> li classpage_item page-item-1422>a hrefhttp://retroramblings.net/?page_id1422>Minimig AGA / RTG/a>/li> li classpage_item page-item-276>a hrefhttp://retroramblings.net/?page_id276>Minimig ECS/a>/li> li classpage_item page-item-1925>a hrefhttp://retroramblings.net/?page_id1925>PET2001/a>/li> li classpage_item page-item-1765>a hrefhttp://retroramblings.net/?page_id1765>VIC20/a>/li> li classpage_item page-item-1880>a hrefhttp://retroramblings.net/?page_id1880>ZX Spectrum 128k core for Turbo Chameleon 64/a>/li> /ul>/li> li classpage_item page-item-1904 page_item_has_children>a hrefhttp://retroramblings.net/?page_id1904>Games Console Cores/a> ul classchildren> li classpage_item page-item-1700>a hrefhttp://retroramblings.net/?page_id1700>Game Boy core/a>/li> li classpage_item page-item-1913>a hrefhttp://retroramblings.net/?page_id1913>Intellivision core/a>/li> li classpage_item page-item-1554>a hrefhttp://retroramblings.net/?page_id1554>Master System core/a>/li> li classpage_item page-item-1604>a hrefhttp://retroramblings.net/?page_id1604>Megadrive / Genesis core/a>/li> li classpage_item page-item-1999>a hrefhttp://retroramblings.net/?page_id1999>Neo Geo core for TC64/a>/li> li classpage_item page-item-1527>a hrefhttp://retroramblings.net/?page_id1527>NES core/a>/li> li classpage_item page-item-1591>a hrefhttp://retroramblings.net/?page_id1591>Vectrex core/a>/li> li classpage_item page-item-969>a hrefhttp://retroramblings.net/?page_id969>TurboGrafx16 / PC Engine/a>/li> /ul>/li>/ul>/li>/ul>/div> /nav>!-- #access --> /header>!-- #branding --> div idmain> div idprimary> div idcontent rolemain> nav idnav-above> h3 classassistive-text>Post navigation/h3> div classnav-previous>a hrefhttp://retroramblings.net/?paged2>span classmeta-nav>←/span> Older posts/a>/div> div classnav-next>/div> /nav>!-- #nav-above --> article idpost-2020 classpost-2020 post type-post status-publish format-standard hentry category-amiga category-fpga category-hardware> header classentry-header> h1 classentry-title>a hrefhttp://retroramblings.net/?p2020 relbookmark>Don’t assume – measure!/a>/h1> div classentry-meta> span classsep>Posted on /span>a hrefhttp://retroramblings.net/?p2020 title12:55 pm relbookmark>time classentry-date datetime2024-08-30T12:55:22+00:00>August 30, 2024/time>/a>span classby-author> span classsep> by /span> span classauthor vcard>a classurl fn n hrefhttp://retroramblings.net/?author2 titleView all posts by AMR relauthor>AMR/a>/span>/span> /div>!-- .entry-meta --> div classcomments-link> a hrefhttp://retroramblings.net/?p2020#respond>span classleave-reply>Reply/span>/a> /div> /header>!-- .entry-header --> div classentry-content> p>This is my first blog post in more than eighteen months, and while I’ve not been nearly as active tech-wise as previously, I am still porting cores to the Turbo Chameleon 64 (see https://www.patreon.com/coresforchameleon), and more recently I was kindly offered a prototype of the new SiDi128./p>p>Normally I’d have declined, since most of the new FPGA platforms are far too complex for my tastes – but SiDi128 is oldskool. No Linux subsystem here – instead there’s an ARM microcontroller running a tight baremetal firmware which is an evolution of that used on the MiST, which itself can trace its origins back to the original Minimig. The FPGA is nice and big (nearly five times the size of the one on MiST) and the board has dual independent SDRAMs. In other words, a nice incremental improvement on the MiST without an explosion in complexity./p>p>Slingshot on atari-forum, who is the primary core developer on MiST and SiDi128, had already ported the Minimig core to the new platform, and added support for the dual SDRAMs, placing Chip RAM, Kickstart, and slow RAM in one chip, and fast RAM in the other./p>p>The expectation was that this would yield a nice performance boost – but it didn’t./p> a hrefhttp://retroramblings.net/?p2020#more-2020 classmore-link>Continue reading span classmeta-nav>→/span>/a> /div>!-- .entry-content --> footer classentry-meta> span classcat-links> span classentry-utility-prep entry-utility-prep-cat-links>Posted in/span> a hrefhttp://retroramblings.net/?cat3 relcategory>Amiga/a>, a hrefhttp://retroramblings.net/?cat4 relcategory>FPGA/a>, a hrefhttp://retroramblings.net/?cat8 relcategory>Hardware/a> /span> span classsep> | /span> span classcomments-link>a hrefhttp://retroramblings.net/?p2020#respond>span classleave-reply>Leave a reply/span>/a>/span> /footer>!-- .entry-meta --> /article>!-- #post-2020 --> article idpost-1946 classpost-1946 post type-post status-publish format-standard hentry category-eightthirtytwo category-fpga category-geekery category-music> header classentry-header> h1 classentry-title>a hrefhttp://retroramblings.net/?p1946 relbookmark>Of ByteBeat, weak linkage and compiler magic/a>/h1> div classentry-meta> span classsep>Posted on /span>a hrefhttp://retroramblings.net/?p1946 title10:12 pm relbookmark>time classentry-date datetime2023-01-17T22:12:14+00:00>January 17, 2023/time>/a>span classby-author> span classsep> by /span> span classauthor vcard>a classurl fn n hrefhttp://retroramblings.net/?author2 titleView all posts by AMR relauthor>AMR/a>/span>/span> /div>!-- .entry-meta --> div classcomments-link> a hrefhttp://retroramblings.net/?p1946#comments>1/a> /div> /header>!-- .entry-header --> div classentry-content> p>I recently came across some very interesting one-line programs, which generate some primitive music from simple logic expressions – a genre which has come to be known as “bytebeat”./p>p>Being in need of a pointless-but-fun project requiring little to no concentration, I immediately wanted to play with these programs. Implementing the logic directly in an FPGA would be perfectly possible, but I actually chose not to this time – instead I wanted to compile them for the EightThirtyTwo CPU and run the sound through the four-channel DMA sound “chip” contained in EightThirtyTwoDemos (modeled very much after the Amiga’s beloved Paula chip!)./p> a hrefhttp://retroramblings.net/?p1946#more-1946 classmore-link>Continue reading span classmeta-nav>→/span>/a> /div>!-- .entry-content --> footer classentry-meta> span classcat-links> span classentry-utility-prep entry-utility-prep-cat-links>Posted in/span> a hrefhttp://retroramblings.net/?cat12 relcategory>EightThirtyTwo/a>, a hrefhttp://retroramblings.net/?cat4 relcategory>FPGA/a>, a hrefhttp://retroramblings.net/?cat9 relcategory>Geekery/a>, a hrefhttp://retroramblings.net/?cat7 relcategory>Music/a> /span> span classsep> | /span> span classcomments-link>a hrefhttp://retroramblings.net/?p1946#comments>b>1/b> Reply/a>/span> /footer>!-- .entry-meta --> /article>!-- #post-1946 --> article idpost-1917 classpost-1917 post type-post status-publish format-standard hentry category-fpga category-linux> header classentry-header> h1 classentry-title>a hrefhttp://retroramblings.net/?p1917 relbookmark>Installing Lattice Diamond on Mint 20.3/a>/h1> div classentry-meta> span classsep>Posted on /span>a hrefhttp://retroramblings.net/?p1917 title9:28 pm relbookmark>time classentry-date datetime2022-06-21T21:28:13+00:00>June 21, 2022/time>/a>span classby-author> span classsep> by /span> span classauthor vcard>a classurl fn n hrefhttp://retroramblings.net/?author2 titleView all posts by AMR relauthor>AMR/a>/span>/span> /div>!-- .entry-meta --> div classcomments-link> a hrefhttp://retroramblings.net/?p1917#comments>1/a> /div> /header>!-- .entry-header --> div classentry-content> p>I’ve been exploring Yosys / NextPnR / Project Trellis on some Lattice ECP5-based boards recently, and I’ve been very impressed and enthused by what I’ve seen. I do have to admit, though, that it’s not “there” yet, especially when it comes to SystemVerilog and VHDL support through the ghdl-yosys-plugin. Yes, you can develop and compile “real” projects with Yosys and friends, but you do have to keep the toolchain’s limitations in mind and design around them./p>p>For this reason I wanted to install and try the “official” software for ECP5 development, namely Lattice Diamond. This left me with a slight problem in that it’s only available on Windows and Redhat Enterprise Linux 6 or 7, with the software distributed in RPM format./p> a hrefhttp://retroramblings.net/?p1917#more-1917 classmore-link>Continue reading span classmeta-nav>→/span>/a> /div>!-- .entry-content --> footer classentry-meta> span classcat-links> span classentry-utility-prep entry-utility-prep-cat-links>Posted in/span> a hrefhttp://retroramblings.net/?cat4 relcategory>FPGA/a>, a hrefhttp://retroramblings.net/?cat13 relcategory>Linux/a> /span> span classsep> | /span> span classcomments-link>a hrefhttp://retroramblings.net/?p1917#comments>b>1/b> Reply/a>/span> /footer>!-- .entry-meta --> /article>!-- #post-1917 --> article idpost-1885 classpost-1885 post type-post status-publish format-standard hentry category-fpga category-geekery category-hardware> header classentry-header> h1 classentry-title>a hrefhttp://retroramblings.net/?p1885 relbookmark>Ports, PMODs and Pin Numbering/a>/h1> div classentry-meta> span classsep>Posted on /span>a hrefhttp://retroramblings.net/?p1885 title4:54 pm relbookmark>time classentry-date datetime2022-05-14T16:54:56+00:00>May 14, 2022/time>/a>span classby-author> span classsep> by /span> span classauthor vcard>a classurl fn n hrefhttp://retroramblings.net/?author2 titleView all posts by AMR relauthor>AMR/a>/span>/span> /div>!-- .entry-meta --> div classcomments-link> a hrefhttp://retroramblings.net/?p1885#respond>span classleave-reply>Reply/span>/a> /div> /header>!-- .entry-header --> div classentry-content> p>strong>2022-05-14/strong>/p>p>Continuing my experiments with the IceSugar-Pro board, building cores using Yosys and friends, I now have EightThirtyTwoDemos running, using PMODs to provide VGA out, I2S audio out, PS/2 keyboard and mouse, and SD card. (The latter isn’t strictly necessary since the FPGA board already has an SD card slot – but it’s on the underside of the board and impossible to access while the IceSugar-Pro is inserted into the carrier board.)/p>p>So how did I go about wiring up the PMODs?/p> a hrefhttp://retroramblings.net/?p1885#more-1885 classmore-link>Continue reading span classmeta-nav>→/span>/a> /div>!-- .entry-content --> footer classentry-meta> span classcat-links> span classentry-utility-prep entry-utility-prep-cat-links>Posted in/span> a hrefhttp://retroramblings.net/?cat4 relcategory>FPGA/a>, a hrefhttp://retroramblings.net/?cat9 relcategory>Geekery/a>, a hrefhttp://retroramblings.net/?cat8 relcategory>Hardware/a> /span> span classsep> | /span> span classcomments-link>a hrefhttp://retroramblings.net/?p1885#respond>span classleave-reply>Leave a reply/span>/a>/span> /footer>!-- .entry-meta --> /article>!-- #post-1885 --> article idpost-1877 classpost-1877 post type-post status-publish format-standard hentry category-eightthirtytwo category-fpga category-geekery> header classentry-header> h1 classentry-title>a hrefhttp://retroramblings.net/?p1877 relbookmark>Found it!/a>/h1> div classentry-meta> span classsep>Posted on /span>a hrefhttp://retroramblings.net/?p1877 title9:19 pm relbookmark>time classentry-date datetime2022-04-28T21:19:15+00:00>April 28, 2022/time>/a>span classby-author> span classsep> by /span> span classauthor vcard>a classurl fn n hrefhttp://retroramblings.net/?author2 titleView all posts by AMR relauthor>AMR/a>/span>/span> /div>!-- .entry-meta --> div classcomments-link> a hrefhttp://retroramblings.net/?p1877#respond>span classleave-reply>Reply/span>/a> /div> /header>!-- .entry-header --> div classentry-content> p>strong>Coping without SignalTap – Part 3 – 2022-04-28/strong>/p>p>I’ve found the bug which was preventing interrupts from working with the EightThirtyTwo CPU, at least in the EightThirtyTwoDemos projects…/p> a hrefhttp://retroramblings.net/?p1877#more-1877 classmore-link>Continue reading span classmeta-nav>→/span>/a> /div>!-- .entry-content --> footer classentry-meta> span classcat-links> span classentry-utility-prep entry-utility-prep-cat-links>Posted in/span> a hrefhttp://retroramblings.net/?cat12 relcategory>EightThirtyTwo/a>, a hrefhttp://retroramblings.net/?cat4 relcategory>FPGA/a>, a hrefhttp://retroramblings.net/?cat9 relcategory>Geekery/a> /span> span classsep> | /span> span classcomments-link>a hrefhttp://retroramblings.net/?p1877#respond>span classleave-reply>Leave a reply/span>/a>/span> /footer>!-- .entry-meta --> /article>!-- #post-1877 --> article idpost-1872 classpost-1872 post type-post status-publish format-standard hentry category-fpga category-geekery> header classentry-header> h1 classentry-title>a hrefhttp://retroramblings.net/?p1872 relbookmark>Triggering a capture/a>/h1> div classentry-meta> span classsep>Posted on /span>a hrefhttp://retroramblings.net/?p1872 title7:18 pm relbookmark>time classentry-date datetime2022-04-26T19:18:55+00:00>April 26, 2022/time>/a>span classby-author> span classsep> by /span> span classauthor vcard>a classurl fn n hrefhttp://retroramblings.net/?author2 titleView all posts by AMR relauthor>AMR/a>/span>/span> /div>!-- .entry-meta --> div classcomments-link> a hrefhttp://retroramblings.net/?p1872#respond>span classleave-reply>Reply/span>/a> /div> /header>!-- .entry-header --> div classentry-content> p>strong>Coping without Signaltap – Part 2 – 2022-04-26/strong>/p>p>By the end of part 1 I was able to communicate over JTAG with a design running on the IceSugarPro, remotely control the LEDs on the board and read the contents of a wide register through a FIFO queue./p>p>That’s the barebones of a useful debugging subsystem, but to be truly useful we need the ability to set a trigger condition./p> a hrefhttp://retroramblings.net/?p1872#more-1872 classmore-link>Continue reading span classmeta-nav>→/span>/a> /div>!-- .entry-content --> footer classentry-meta> span classcat-links> span classentry-utility-prep entry-utility-prep-cat-links>Posted in/span> a hrefhttp://retroramblings.net/?cat4 relcategory>FPGA/a>, a hrefhttp://retroramblings.net/?cat9 relcategory>Geekery/a> /span> span classsep> | /span> span classcomments-link>a hrefhttp://retroramblings.net/?p1872#respond>span classleave-reply>Leave a reply/span>/a>/span> /footer>!-- .entry-meta --> /article>!-- #post-1872 --> article idpost-1870 classpost-1870 post type-post status-publish format-standard hentry category-fpga category-geekery category-hardware> header classentry-header> h1 classentry-title>a hrefhttp://retroramblings.net/?p1870 relbookmark>Coping without SignalTap/a>/h1> div classentry-meta> span classsep>Posted on /span>a hrefhttp://retroramblings.net/?p1870 title10:14 pm relbookmark>time classentry-date datetime2022-04-19T22:14:28+00:00>April 19, 2022/time>/a>span classby-author> span classsep> by /span> span classauthor vcard>a classurl fn n hrefhttp://retroramblings.net/?author2 titleView all posts by AMR relauthor>AMR/a>/span>/span> /div>!-- .entry-meta --> div classcomments-link> a hrefhttp://retroramblings.net/?p1870#respond>span classleave-reply>Reply/span>/a> /div> /header>!-- .entry-header --> div classentry-content> p>strong>2022-04-19 – Part 1: Establishing communication/strong>/p>p>If I’m going to find the problem with EightThirtyTwo that’s preventing interrupts from working, I’m going to need some way of observing what’s going on. The CPU works in GHDL Simulation, works on Altera/Intel chips, and works on Xilinx chips so there must be something I’m doing which the Open Source toolchain doesn’t like. (Or I may have stumbled upon an actual bug…)/p>p>There are basically three problems to solve here:/p>ul classwp-block-list>li>Capturing the state of internal signals/li>li>Transporting those signals to the host computer/li>li>Displaying them in a meaningful and readable format./li>/ul> a hrefhttp://retroramblings.net/?p1870#more-1870 classmore-link>Continue reading span classmeta-nav>→/span>/a> /div>!-- .entry-content --> footer classentry-meta> span classcat-links> span classentry-utility-prep entry-utility-prep-cat-links>Posted in/span> a hrefhttp://retroramblings.net/?cat4 relcategory>FPGA/a>, a hrefhttp://retroramblings.net/?cat9 relcategory>Geekery/a>, a hrefhttp://retroramblings.net/?cat8 relcategory>Hardware/a> /span> span classsep> | /span> span classcomments-link>a hrefhttp://retroramblings.net/?p1870#respond>span classleave-reply>Leave a reply/span>/a>/span> /footer>!-- .entry-meta --> /article>!-- #post-1870 --> article idpost-1866 classpost-1866 post type-post status-publish format-standard hentry category-fpga category-geekery category-hardware> header classentry-header> h1 classentry-title>a hrefhttp://retroramblings.net/?p1866 relbookmark>Exploring Yosys/Trellis/NextPnR for Lattice ECP5/a>/h1> div classentry-meta> span classsep>Posted on /span>a hrefhttp://retroramblings.net/?p1866 title3:21 pm relbookmark>time classentry-date datetime2022-04-18T15:21:53+00:00>April 18, 2022/time>/a>span classby-author> span classsep> by /span> span classauthor vcard>a classurl fn n hrefhttp://retroramblings.net/?author2 titleView all posts by AMR relauthor>AMR/a>/span>/span> /div>!-- .entry-meta --> div classcomments-link> a hrefhttp://retroramblings.net/?p1866#respond>span classleave-reply>Reply/span>/a> /div> /header>!-- .entry-header --> div classentry-content> p>strong>2022-04-18/strong>/p>p>I’ve been tinkering with the IceSugarPro board recently, which is a nice little SO-DIMM form factor FPGA board containing a Lattice ECP5 FPGA. It’s the successor to the earlier IceSugar board which contained a Lattice iCE40UP5k: despite not having an iCE40 series chip, the IceSugarPro retains the name!/p> a hrefhttp://retroramblings.net/?p1866#more-1866 classmore-link>Continue reading span classmeta-nav>→/span>/a> /div>!-- .entry-content --> footer classentry-meta> span classcat-links> span classentry-utility-prep entry-utility-prep-cat-links>Posted in/span> a hrefhttp://retroramblings.net/?cat4 relcategory>FPGA/a>, a hrefhttp://retroramblings.net/?cat9 relcategory>Geekery/a>, a hrefhttp://retroramblings.net/?cat8 relcategory>Hardware/a> /span> span classsep> | /span> span classcomments-link>a hrefhttp://retroramblings.net/?p1866#respond>span classleave-reply>Leave a reply/span>/a>/span> /footer>!-- .entry-meta --> /article>!-- #post-1866 --> article idpost-1861 classpost-1861 post type-post status-publish format-standard hentry category-fpga category-hardware> header classentry-header> h1 classentry-title>a hrefhttp://retroramblings.net/?p1861 relbookmark>It’s only just dawned on me…/a>/h1> div classentry-meta> span classsep>Posted on /span>a hrefhttp://retroramblings.net/?p1861 title9:26 pm relbookmark>time classentry-date datetime2022-03-31T21:26:16+00:00>March 31, 2022/time>/a>span classby-author> span classsep> by /span> span classauthor vcard>a classurl fn n hrefhttp://retroramblings.net/?author2 titleView all posts by AMR relauthor>AMR/a>/span>/span> /div>!-- .entry-meta --> div classcomments-link> a hrefhttp://retroramblings.net/?p1861#comments>1/a> /div> /header>!-- .entry-header --> div classentry-content> p>… that the reason for the “I$” and “D$” notation when discussing instruction and data caches is the homonym between “cache” and “cash”! Now I feel very dim!/p> /div>!-- .entry-content --> footer classentry-meta> span classcat-links> span classentry-utility-prep entry-utility-prep-cat-links>Posted in/span> a hrefhttp://retroramblings.net/?cat4 relcategory>FPGA/a>, a hrefhttp://retroramblings.net/?cat8 relcategory>Hardware/a> /span> span classsep> | /span> span classcomments-link>a hrefhttp://retroramblings.net/?p1861#comments>b>1/b> Reply/a>/span> /footer>!-- .entry-meta --> /article>!-- #post-1861 --> article idpost-1854 classpost-1854 post type-post status-publish format-standard hentry category-eightthirtytwo category-fpga category-geekery category-hardware category-linux> header classentry-header> h1 classentry-title>a hrefhttp://retroramblings.net/?p1854 relbookmark>JTAG and Tcl – twin rabbitholes!/a>/h1> div classentry-meta> span classsep>Posted on /span>a hrefhttp://retroramblings.net/?p1854 title5:44 pm relbookmark>time classentry-date datetime2022-03-29T17:44:12+00:00>March 29, 2022/time>/a>span classby-author> span classsep> by /span> span classauthor vcard>a classurl fn n hrefhttp://retroramblings.net/?author2 titleView all posts by AMR relauthor>AMR/a>/span>/span> /div>!-- .entry-meta --> div classcomments-link> a hrefhttp://retroramblings.net/?p1854#respond>span classleave-reply>Reply/span>/a> /div> /header>!-- .entry-header --> div classentry-content> p>strong>2022-03-29/strong>/p>p>I’ve been experimenting with the QMTech Kintex7 board, which provides a huge FPGA for a less huge amount of money. The one thing that prevents my existing projects from running on it without deep changes is the lack of SDRAM, but since I’ve been wanting to get more familiar with the Xilinx ecosystem for a while, this was a good opportunity to dive in./p> a hrefhttp://retroramblings.net/?p1854#more-1854 classmore-link>Continue reading span classmeta-nav>→/span>/a> /div>!-- .entry-content --> footer classentry-meta> span classcat-links> span classentry-utility-prep entry-utility-prep-cat-links>Posted in/span> a hrefhttp://retroramblings.net/?cat12 relcategory>EightThirtyTwo/a>, a hrefhttp://retroramblings.net/?cat4 relcategory>FPGA/a>, a hrefhttp://retroramblings.net/?cat9 relcategory>Geekery/a>, a hrefhttp://retroramblings.net/?cat8 relcategory>Hardware/a>, a hrefhttp://retroramblings.net/?cat13 relcategory>Linux/a> /span> span classsep> | /span> span classcomments-link>a hrefhttp://retroramblings.net/?p1854#respond>span classleave-reply>Leave a reply/span>/a>/span> /footer>!-- .entry-meta --> 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classpage_item page-item-945>a hrefhttps://retroramblings.net/?page_id945>Links and Resources/a>/li>/ul>/li>li classpage_item page-item-1377 page_item_has_children>a hrefhttps://retroramblings.net/?page_id1377>Turbo Chameleon 64/a>ul classchildren> li classpage_item page-item-1380>a hrefhttps://retroramblings.net/?page_id1380>Arcade Cores/a>/li> li classpage_item page-item-1894 page_item_has_children>a hrefhttps://retroramblings.net/?page_id1894>Computer cores/a> ul classchildren> li classpage_item page-item-1859>a hrefhttps://retroramblings.net/?page_id1859>Amstrad CPC464/6128 for Turbo Chameleon 64/a>/li> li classpage_item page-item-1984>a hrefhttps://retroramblings.net/?page_id1984>Archimedes core for Turbo Chameleon 64/a>/li> li classpage_item page-item-1705>a hrefhttps://retroramblings.net/?page_id1705>Atari ST (MiSTery)/a>/li> li classpage_item page-item-1841>a hrefhttps://retroramblings.net/?page_id1841>BBC Micro/a>/li> li classpage_item page-item-1612>a hrefhttps://retroramblings.net/?page_id1612>Commodore 16 / Plus 4/a>/li> li classpage_item page-item-1989>a hrefhttps://retroramblings.net/?page_id1989>IBM PC/XT core for Turbo Chameleon 64/a>/li> li classpage_item page-item-1422>a hrefhttps://retroramblings.net/?page_id1422>Minimig AGA / RTG/a>/li> li classpage_item page-item-276>a hrefhttps://retroramblings.net/?page_id276>Minimig ECS/a>/li> li classpage_item page-item-1925>a hrefhttps://retroramblings.net/?page_id1925>PET2001/a>/li> li classpage_item page-item-1765>a hrefhttps://retroramblings.net/?page_id1765>VIC20/a>/li> li classpage_item page-item-1880>a hrefhttps://retroramblings.net/?page_id1880>ZX Spectrum 128k core for Turbo Chameleon 64/a>/li> /ul>/li> li classpage_item page-item-1904 page_item_has_children>a hrefhttps://retroramblings.net/?page_id1904>Games Console Cores/a> ul classchildren> li classpage_item page-item-1700>a hrefhttps://retroramblings.net/?page_id1700>Game Boy core/a>/li> li classpage_item page-item-1913>a hrefhttps://retroramblings.net/?page_id1913>Intellivision core/a>/li> li classpage_item page-item-1554>a hrefhttps://retroramblings.net/?page_id1554>Master System core/a>/li> li classpage_item page-item-1604>a hrefhttps://retroramblings.net/?page_id1604>Megadrive / Genesis core/a>/li> li classpage_item page-item-1999>a hrefhttps://retroramblings.net/?page_id1999>Neo Geo core for TC64/a>/li> li classpage_item page-item-1527>a hrefhttps://retroramblings.net/?page_id1527>NES core/a>/li> li classpage_item page-item-1591>a hrefhttps://retroramblings.net/?page_id1591>Vectrex core/a>/li> li classpage_item page-item-969>a hrefhttps://retroramblings.net/?page_id969>TurboGrafx16 / PC Engine/a>/li> /ul>/li>/ul>/li>/ul>/div> /nav>!-- #access --> /header>!-- #branding --> div idmain> div idprimary> div idcontent rolemain> nav idnav-above> h3 classassistive-text>Post navigation/h3> div classnav-previous>a hrefhttps://retroramblings.net/?paged2>span classmeta-nav>←/span> Older posts/a>/div> div classnav-next>/div> /nav>!-- #nav-above --> article idpost-2020 classpost-2020 post type-post status-publish format-standard hentry category-amiga category-fpga category-hardware> header classentry-header> h1 classentry-title>a hrefhttps://retroramblings.net/?p2020 relbookmark>Don’t assume – measure!/a>/h1> div classentry-meta> span classsep>Posted on /span>a hrefhttps://retroramblings.net/?p2020 title12:55 pm relbookmark>time classentry-date datetime2024-08-30T12:55:22+00:00>August 30, 2024/time>/a>span classby-author> span classsep> by /span> span classauthor vcard>a classurl fn n hrefhttps://retroramblings.net/?author2 titleView all posts by AMR relauthor>AMR/a>/span>/span> /div>!-- .entry-meta --> div classcomments-link> a hrefhttps://retroramblings.net/?p2020#respond>span classleave-reply>Reply/span>/a> /div> /header>!-- .entry-header --> div classentry-content> p>This is my first blog post in more than eighteen months, and while I’ve not been nearly as active tech-wise as previously, I am still porting cores to the Turbo Chameleon 64 (see https://www.patreon.com/coresforchameleon), and more recently I was kindly offered a prototype of the new SiDi128./p>p>Normally I’d have declined, since most of the new FPGA platforms are far too complex for my tastes – but SiDi128 is oldskool. No Linux subsystem here – instead there’s an ARM microcontroller running a tight baremetal firmware which is an evolution of that used on the MiST, which itself can trace its origins back to the original Minimig. The FPGA is nice and big (nearly five times the size of the one on MiST) and the board has dual independent SDRAMs. In other words, a nice incremental improvement on the MiST without an explosion in complexity./p>p>Slingshot on atari-forum, who is the primary core developer on MiST and SiDi128, had already ported the Minimig core to the new platform, and added support for the dual SDRAMs, placing Chip RAM, Kickstart, and slow RAM in one chip, and fast RAM in the other./p>p>The expectation was that this would yield a nice performance boost – but it didn’t./p> a hrefhttps://retroramblings.net/?p2020#more-2020 classmore-link>Continue reading span classmeta-nav>→/span>/a> /div>!-- .entry-content --> footer classentry-meta> span classcat-links> span classentry-utility-prep entry-utility-prep-cat-links>Posted in/span> a hrefhttps://retroramblings.net/?cat3 relcategory>Amiga/a>, a hrefhttps://retroramblings.net/?cat4 relcategory>FPGA/a>, a hrefhttps://retroramblings.net/?cat8 relcategory>Hardware/a> /span> span classsep> | /span> span classcomments-link>a hrefhttps://retroramblings.net/?p2020#respond>span classleave-reply>Leave a reply/span>/a>/span> /footer>!-- .entry-meta --> /article>!-- #post-2020 --> article idpost-1946 classpost-1946 post type-post status-publish format-standard hentry category-eightthirtytwo category-fpga category-geekery category-music> header classentry-header> h1 classentry-title>a hrefhttps://retroramblings.net/?p1946 relbookmark>Of ByteBeat, weak linkage and compiler magic/a>/h1> div classentry-meta> span classsep>Posted on /span>a hrefhttps://retroramblings.net/?p1946 title10:12 pm relbookmark>time classentry-date datetime2023-01-17T22:12:14+00:00>January 17, 2023/time>/a>span classby-author> span classsep> by /span> span classauthor vcard>a classurl fn n hrefhttps://retroramblings.net/?author2 titleView all posts by AMR relauthor>AMR/a>/span>/span> /div>!-- .entry-meta --> div classcomments-link> a hrefhttps://retroramblings.net/?p1946#comments>1/a> /div> /header>!-- .entry-header --> div classentry-content> p>I recently came across some very interesting one-line programs, which generate some primitive music from simple logic expressions – a genre which has come to be known as “bytebeat”./p>p>Being in need of a pointless-but-fun project requiring little to no concentration, I immediately wanted to play with these programs. Implementing the logic directly in an FPGA would be perfectly possible, but I actually chose not to this time – instead I wanted to compile them for the EightThirtyTwo CPU and run the sound through the four-channel DMA sound “chip” contained in EightThirtyTwoDemos (modeled very much after the Amiga’s beloved Paula chip!)./p> a hrefhttps://retroramblings.net/?p1946#more-1946 classmore-link>Continue reading span classmeta-nav>→/span>/a> /div>!-- .entry-content --> footer classentry-meta> span classcat-links> span classentry-utility-prep entry-utility-prep-cat-links>Posted in/span> a hrefhttps://retroramblings.net/?cat12 relcategory>EightThirtyTwo/a>, a hrefhttps://retroramblings.net/?cat4 relcategory>FPGA/a>, a hrefhttps://retroramblings.net/?cat9 relcategory>Geekery/a>, a hrefhttps://retroramblings.net/?cat7 relcategory>Music/a> /span> span classsep> | /span> span classcomments-link>a hrefhttps://retroramblings.net/?p1946#comments>b>1/b> Reply/a>/span> /footer>!-- .entry-meta --> /article>!-- #post-1946 --> article idpost-1917 classpost-1917 post type-post status-publish format-standard hentry category-fpga category-linux> header classentry-header> h1 classentry-title>a hrefhttps://retroramblings.net/?p1917 relbookmark>Installing Lattice Diamond on Mint 20.3/a>/h1> div classentry-meta> span classsep>Posted on /span>a hrefhttps://retroramblings.net/?p1917 title9:28 pm relbookmark>time classentry-date datetime2022-06-21T21:28:13+00:00>June 21, 2022/time>/a>span classby-author> span classsep> by /span> span classauthor vcard>a classurl fn n hrefhttps://retroramblings.net/?author2 titleView all posts by AMR relauthor>AMR/a>/span>/span> /div>!-- .entry-meta --> div classcomments-link> a hrefhttps://retroramblings.net/?p1917#comments>1/a> /div> /header>!-- .entry-header --> div classentry-content> p>I’ve been exploring Yosys / NextPnR / Project Trellis on some Lattice ECP5-based boards recently, and I’ve been very impressed and enthused by what I’ve seen. I do have to admit, though, that it’s not “there” yet, especially when it comes to SystemVerilog and VHDL support through the ghdl-yosys-plugin. Yes, you can develop and compile “real” projects with Yosys and friends, but you do have to keep the toolchain’s limitations in mind and design around them./p>p>For this reason I wanted to install and try the “official” software for ECP5 development, namely Lattice Diamond. This left me with a slight problem in that it’s only available on Windows and Redhat Enterprise Linux 6 or 7, with the software distributed in RPM format./p> a hrefhttps://retroramblings.net/?p1917#more-1917 classmore-link>Continue reading span classmeta-nav>→/span>/a> /div>!-- .entry-content --> footer classentry-meta> span classcat-links> span classentry-utility-prep entry-utility-prep-cat-links>Posted in/span> a hrefhttps://retroramblings.net/?cat4 relcategory>FPGA/a>, a hrefhttps://retroramblings.net/?cat13 relcategory>Linux/a> /span> span classsep> | /span> span classcomments-link>a hrefhttps://retroramblings.net/?p1917#comments>b>1/b> Reply/a>/span> /footer>!-- .entry-meta --> /article>!-- #post-1917 --> article idpost-1885 classpost-1885 post type-post status-publish format-standard hentry category-fpga category-geekery category-hardware> header classentry-header> h1 classentry-title>a hrefhttps://retroramblings.net/?p1885 relbookmark>Ports, PMODs and Pin Numbering/a>/h1> div classentry-meta> span classsep>Posted on /span>a hrefhttps://retroramblings.net/?p1885 title4:54 pm relbookmark>time classentry-date datetime2022-05-14T16:54:56+00:00>May 14, 2022/time>/a>span classby-author> span classsep> by /span> span classauthor vcard>a classurl fn n hrefhttps://retroramblings.net/?author2 titleView all posts by AMR relauthor>AMR/a>/span>/span> /div>!-- .entry-meta --> div classcomments-link> a hrefhttps://retroramblings.net/?p1885#respond>span classleave-reply>Reply/span>/a> /div> /header>!-- .entry-header --> div classentry-content> p>strong>2022-05-14/strong>/p>p>Continuing my experiments with the IceSugar-Pro board, building cores using Yosys and friends, I now have EightThirtyTwoDemos running, using PMODs to provide VGA out, I2S audio out, PS/2 keyboard and mouse, and SD card. (The latter isn’t strictly necessary since the FPGA board already has an SD card slot – but it’s on the underside of the board and impossible to access while the IceSugar-Pro is inserted into the carrier board.)/p>p>So how did I go about wiring up the PMODs?/p> a hrefhttps://retroramblings.net/?p1885#more-1885 classmore-link>Continue reading span classmeta-nav>→/span>/a> /div>!-- .entry-content --> footer classentry-meta> span classcat-links> span classentry-utility-prep entry-utility-prep-cat-links>Posted in/span> a hrefhttps://retroramblings.net/?cat4 relcategory>FPGA/a>, a hrefhttps://retroramblings.net/?cat9 relcategory>Geekery/a>, a hrefhttps://retroramblings.net/?cat8 relcategory>Hardware/a> /span> span classsep> | /span> span classcomments-link>a hrefhttps://retroramblings.net/?p1885#respond>span classleave-reply>Leave a reply/span>/a>/span> /footer>!-- .entry-meta --> /article>!-- #post-1885 --> article idpost-1877 classpost-1877 post type-post status-publish format-standard hentry category-eightthirtytwo category-fpga category-geekery> header classentry-header> h1 classentry-title>a hrefhttps://retroramblings.net/?p1877 relbookmark>Found it!/a>/h1> div classentry-meta> span classsep>Posted on /span>a hrefhttps://retroramblings.net/?p1877 title9:19 pm relbookmark>time classentry-date datetime2022-04-28T21:19:15+00:00>April 28, 2022/time>/a>span classby-author> span classsep> by /span> span classauthor vcard>a classurl fn n hrefhttps://retroramblings.net/?author2 titleView all posts by AMR relauthor>AMR/a>/span>/span> /div>!-- .entry-meta --> div classcomments-link> a hrefhttps://retroramblings.net/?p1877#respond>span classleave-reply>Reply/span>/a> /div> /header>!-- .entry-header --> div classentry-content> p>strong>Coping without SignalTap – Part 3 – 2022-04-28/strong>/p>p>I’ve found the bug which was preventing interrupts from working with the EightThirtyTwo CPU, at least in the EightThirtyTwoDemos projects…/p> a hrefhttps://retroramblings.net/?p1877#more-1877 classmore-link>Continue reading span classmeta-nav>→/span>/a> /div>!-- .entry-content --> footer classentry-meta> span classcat-links> span classentry-utility-prep entry-utility-prep-cat-links>Posted in/span> a hrefhttps://retroramblings.net/?cat12 relcategory>EightThirtyTwo/a>, a hrefhttps://retroramblings.net/?cat4 relcategory>FPGA/a>, a hrefhttps://retroramblings.net/?cat9 relcategory>Geekery/a> /span> span classsep> | /span> span classcomments-link>a hrefhttps://retroramblings.net/?p1877#respond>span classleave-reply>Leave a reply/span>/a>/span> /footer>!-- .entry-meta --> /article>!-- #post-1877 --> article idpost-1872 classpost-1872 post type-post status-publish format-standard hentry category-fpga category-geekery> header classentry-header> h1 classentry-title>a hrefhttps://retroramblings.net/?p1872 relbookmark>Triggering a capture/a>/h1> div classentry-meta> span classsep>Posted on /span>a hrefhttps://retroramblings.net/?p1872 title7:18 pm relbookmark>time classentry-date datetime2022-04-26T19:18:55+00:00>April 26, 2022/time>/a>span classby-author> span classsep> by /span> span classauthor vcard>a classurl fn n hrefhttps://retroramblings.net/?author2 titleView all posts by AMR relauthor>AMR/a>/span>/span> /div>!-- .entry-meta --> div classcomments-link> a hrefhttps://retroramblings.net/?p1872#respond>span classleave-reply>Reply/span>/a> /div> /header>!-- .entry-header --> div classentry-content> p>strong>Coping without Signaltap – Part 2 – 2022-04-26/strong>/p>p>By the end of part 1 I was able to communicate over JTAG with a design running on the IceSugarPro, remotely control the LEDs on the board and read the contents of a wide register through a FIFO queue./p>p>That’s the barebones of a useful debugging subsystem, but to be truly useful we need the ability to set a trigger condition./p> a hrefhttps://retroramblings.net/?p1872#more-1872 classmore-link>Continue reading span classmeta-nav>→/span>/a> /div>!-- .entry-content --> footer classentry-meta> span classcat-links> span classentry-utility-prep entry-utility-prep-cat-links>Posted in/span> a hrefhttps://retroramblings.net/?cat4 relcategory>FPGA/a>, a hrefhttps://retroramblings.net/?cat9 relcategory>Geekery/a> /span> span classsep> | /span> span classcomments-link>a hrefhttps://retroramblings.net/?p1872#respond>span classleave-reply>Leave a reply/span>/a>/span> /footer>!-- .entry-meta --> /article>!-- #post-1872 --> article idpost-1870 classpost-1870 post type-post status-publish format-standard hentry category-fpga category-geekery category-hardware> header classentry-header> h1 classentry-title>a hrefhttps://retroramblings.net/?p1870 relbookmark>Coping without SignalTap/a>/h1> div classentry-meta> span classsep>Posted on /span>a hrefhttps://retroramblings.net/?p1870 title10:14 pm relbookmark>time classentry-date datetime2022-04-19T22:14:28+00:00>April 19, 2022/time>/a>span classby-author> span classsep> by /span> span classauthor vcard>a classurl fn n hrefhttps://retroramblings.net/?author2 titleView all posts by AMR relauthor>AMR/a>/span>/span> /div>!-- .entry-meta --> div classcomments-link> a hrefhttps://retroramblings.net/?p1870#respond>span classleave-reply>Reply/span>/a> /div> /header>!-- .entry-header --> div classentry-content> p>strong>2022-04-19 – Part 1: Establishing communication/strong>/p>p>If I’m going to find the problem with EightThirtyTwo that’s preventing interrupts from working, I’m going to need some way of observing what’s going on. The CPU works in GHDL Simulation, works on Altera/Intel chips, and works on Xilinx chips so there must be something I’m doing which the Open Source toolchain doesn’t like. (Or I may have stumbled upon an actual bug…)/p>p>There are basically three problems to solve here:/p>ul classwp-block-list>li>Capturing the state of internal signals/li>li>Transporting those signals to the host computer/li>li>Displaying them in a meaningful and readable format./li>/ul> a hrefhttps://retroramblings.net/?p1870#more-1870 classmore-link>Continue reading span classmeta-nav>→/span>/a> /div>!-- .entry-content --> footer classentry-meta> span classcat-links> span classentry-utility-prep entry-utility-prep-cat-links>Posted in/span> a hrefhttps://retroramblings.net/?cat4 relcategory>FPGA/a>, a hrefhttps://retroramblings.net/?cat9 relcategory>Geekery/a>, a hrefhttps://retroramblings.net/?cat8 relcategory>Hardware/a> /span> span classsep> | /span> span classcomments-link>a hrefhttps://retroramblings.net/?p1870#respond>span classleave-reply>Leave a reply/span>/a>/span> /footer>!-- .entry-meta --> /article>!-- #post-1870 --> article idpost-1866 classpost-1866 post type-post status-publish format-standard hentry category-fpga category-geekery category-hardware> header classentry-header> h1 classentry-title>a hrefhttps://retroramblings.net/?p1866 relbookmark>Exploring Yosys/Trellis/NextPnR for Lattice ECP5/a>/h1> div classentry-meta> span classsep>Posted on /span>a hrefhttps://retroramblings.net/?p1866 title3:21 pm relbookmark>time classentry-date datetime2022-04-18T15:21:53+00:00>April 18, 2022/time>/a>span classby-author> span classsep> by /span> span classauthor vcard>a classurl fn n hrefhttps://retroramblings.net/?author2 titleView all posts by AMR relauthor>AMR/a>/span>/span> /div>!-- .entry-meta --> div classcomments-link> a hrefhttps://retroramblings.net/?p1866#respond>span classleave-reply>Reply/span>/a> /div> /header>!-- .entry-header --> div classentry-content> p>strong>2022-04-18/strong>/p>p>I’ve been tinkering with the IceSugarPro board recently, which is a nice little SO-DIMM form factor FPGA board containing a Lattice ECP5 FPGA. It’s the successor to the earlier IceSugar board which contained a Lattice iCE40UP5k: despite not having an iCE40 series chip, the IceSugarPro retains the name!/p> a hrefhttps://retroramblings.net/?p1866#more-1866 classmore-link>Continue reading span classmeta-nav>→/span>/a> /div>!-- .entry-content --> footer classentry-meta> span classcat-links> span classentry-utility-prep entry-utility-prep-cat-links>Posted in/span> a hrefhttps://retroramblings.net/?cat4 relcategory>FPGA/a>, a hrefhttps://retroramblings.net/?cat9 relcategory>Geekery/a>, a hrefhttps://retroramblings.net/?cat8 relcategory>Hardware/a> /span> span classsep> | /span> span classcomments-link>a hrefhttps://retroramblings.net/?p1866#respond>span classleave-reply>Leave a reply/span>/a>/span> /footer>!-- .entry-meta --> /article>!-- #post-1866 --> article idpost-1861 classpost-1861 post type-post status-publish format-standard hentry category-fpga category-hardware> header classentry-header> h1 classentry-title>a hrefhttps://retroramblings.net/?p1861 relbookmark>It’s only just dawned on me…/a>/h1> div classentry-meta> span classsep>Posted on /span>a hrefhttps://retroramblings.net/?p1861 title9:26 pm relbookmark>time classentry-date datetime2022-03-31T21:26:16+00:00>March 31, 2022/time>/a>span classby-author> span classsep> by /span> span classauthor vcard>a classurl fn n hrefhttps://retroramblings.net/?author2 titleView all posts by AMR relauthor>AMR/a>/span>/span> /div>!-- .entry-meta --> div classcomments-link> a hrefhttps://retroramblings.net/?p1861#comments>1/a> /div> /header>!-- .entry-header --> div classentry-content> p>… that the reason for the “I$” and “D$” notation when discussing instruction and data caches is the homonym between “cache” and “cash”! Now I feel very dim!/p> /div>!-- .entry-content --> footer classentry-meta> span classcat-links> span classentry-utility-prep entry-utility-prep-cat-links>Posted in/span> a hrefhttps://retroramblings.net/?cat4 relcategory>FPGA/a>, a hrefhttps://retroramblings.net/?cat8 relcategory>Hardware/a> /span> span classsep> | /span> span classcomments-link>a hrefhttps://retroramblings.net/?p1861#comments>b>1/b> Reply/a>/span> /footer>!-- .entry-meta --> /article>!-- #post-1861 --> article idpost-1854 classpost-1854 post type-post status-publish format-standard hentry category-eightthirtytwo category-fpga category-geekery category-hardware category-linux> header classentry-header> h1 classentry-title>a hrefhttps://retroramblings.net/?p1854 relbookmark>JTAG and Tcl – twin rabbitholes!/a>/h1> div classentry-meta> span classsep>Posted on /span>a hrefhttps://retroramblings.net/?p1854 title5:44 pm relbookmark>time classentry-date datetime2022-03-29T17:44:12+00:00>March 29, 2022/time>/a>span classby-author> span classsep> by /span> span classauthor vcard>a classurl fn n hrefhttps://retroramblings.net/?author2 titleView all posts by AMR relauthor>AMR/a>/span>/span> /div>!-- .entry-meta --> div classcomments-link> a hrefhttps://retroramblings.net/?p1854#respond>span classleave-reply>Reply/span>/a> /div> /header>!-- .entry-header --> div classentry-content> p>strong>2022-03-29/strong>/p>p>I’ve been experimenting with the QMTech Kintex7 board, which provides a huge FPGA for a less huge amount of money. The one thing that prevents my existing projects from running on it without deep changes is the lack of SDRAM, but since I’ve been wanting to get more familiar with the Xilinx ecosystem for a while, this was a good opportunity to dive in./p> a hrefhttps://retroramblings.net/?p1854#more-1854 classmore-link>Continue reading span classmeta-nav>→/span>/a> /div>!-- .entry-content --> footer classentry-meta> span classcat-links> span classentry-utility-prep entry-utility-prep-cat-links>Posted in/span> a hrefhttps://retroramblings.net/?cat12 relcategory>EightThirtyTwo/a>, a hrefhttps://retroramblings.net/?cat4 relcategory>FPGA/a>, a hrefhttps://retroramblings.net/?cat9 relcategory>Geekery/a>, a hrefhttps://retroramblings.net/?cat8 relcategory>Hardware/a>, a hrefhttps://retroramblings.net/?cat13 relcategory>Linux/a> /span> span classsep> | /span> span classcomments-link>a hrefhttps://retroramblings.net/?p1854#respond>span classleave-reply>Leave a reply/span>/a>/span> /footer>!-- .entry-meta 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