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Domain > chipdesign.be
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More information on this domain is in
AlienVault OTX
Is this malicious?
Yes
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Whois
Property
Value
NameServer
ns1.cp.hostnet.nl
Created
2012-07-28 00:00:00
Registrar
Hostnet bv
DNS Resolutions
Date
IP Address
2025-01-02
91.184.0.74
(
ClassC
)
Port 80
HTTP/1.1 200 OKServer: nginx/1.24.0Date: Tue, 16 Apr 2024 15:46:58 GMTContent-Type: text/htmlContent-Length: 6830Last-Modified: Fri, 20 Jan 2023 20:42:29 GMTVary: Accept-EncodingETag: 63cafcb5-1aaeAcc !DOCTYPE html>html classno-js langen>head> meta charsetUTF-8> title>ChipDesign Integrated Circuit & Sensor Design/title> link relstylesheet typetext/css hrefcss/main.css> link relicon hrefimages/look&feel/ChipDesign_favicon.png> link hrefhttps://fonts.googleapis.com/css?familyBaloo|Roboto:100,100i,300,300i,400,400i,500,500i,700,700i,900,900i relstylesheet>/head>body>div idlogo>/div>div idhex classheader>/div> div idmenu_div> ul idmenu-bar> li classactive> a hrefindex.html>Services/a> ul> li>a hrefindex.html#ic_design>IC Design/a>/li> li>a hrefindex.html#sensor_design>Sensor Design/a>/li> /ul> /li> li class> a hrefsoftware.html>Open-Source Software/a> ul> li>a hrefsoftware.html#nf2ff>NF2FF/a>/li> li>a hrefsoftware.html#rflib>rfLib/a>/li> li>a hrefsoftware.html#rfmaxima>rfMaxima/a>/li> li>a hrefsoftware.html#verilog-a_rf_mems_models>Verilog-A RF MEMS Models/a>/li> /ul> /li> li class> a hrefpatents.html>Patents, Publications & Short Courses/a> ul> li>a hrefpatents.html#patents>Patents/a>/li> li>a hrefpatents.html#publications>Publications/a>/li> li>a hrefpatents.html#short_courses>Short Courses/a>/li> /ul> /ul>/div>div idcaptioned-gallery> figure classslider> figure> img srcimages/slideshow1.png alt> figcaption>Analog mixed-signal / RF IC designp classparagraph>Using state-of-the-art CMOS processes/p>/figcaption> /figure> figure> img srcimages/slideshow2.png alt> figcaption>Assembly of SoCsp classparagraph>Integration of analog mixed signal, memory and processor IPs/p>/figcaption> /figure> figure> img srcimages/slideshow3.png alt> figcaption>High-voltage IC designp classparagraph>Using BCD processes/p>/figcaption> /figure> figure> img srcimages/slideshow4.png alt> figcaption>MMIC designp classparagraph>Using InGaAs pHEMT and GaN HEMT processes/p>/figcaption> /figure> figure> img srcimages/slideshow1.png alt> fig
Port 443
HTTP/1.1 200 OKServer: nginx/1.24.0Date: Tue, 16 Apr 2024 15:46:59 GMTContent-Type: text/htmlContent-Length: 6830Last-Modified: Fri, 20 Jan 2023 20:42:29 GMTConnection: keep-aliveVary: Accept-Encoding !DOCTYPE html>html classno-js langen>head> meta charsetUTF-8> title>ChipDesign Integrated Circuit & Sensor Design/title> link relstylesheet typetext/css hrefcss/main.css> link relicon hrefimages/look&feel/ChipDesign_favicon.png> link hrefhttps://fonts.googleapis.com/css?familyBaloo|Roboto:100,100i,300,300i,400,400i,500,500i,700,700i,900,900i relstylesheet>/head>body>div idlogo>/div>div idhex classheader>/div> div idmenu_div> ul idmenu-bar> li classactive> a hrefindex.html>Services/a> ul> li>a hrefindex.html#ic_design>IC Design/a>/li> li>a hrefindex.html#sensor_design>Sensor Design/a>/li> /ul> /li> li class> a hrefsoftware.html>Open-Source Software/a> ul> li>a hrefsoftware.html#nf2ff>NF2FF/a>/li> li>a hrefsoftware.html#rflib>rfLib/a>/li> li>a hrefsoftware.html#rfmaxima>rfMaxima/a>/li> li>a hrefsoftware.html#verilog-a_rf_mems_models>Verilog-A RF MEMS Models/a>/li> /ul> /li> li class> a hrefpatents.html>Patents, Publications & Short Courses/a> ul> li>a hrefpatents.html#patents>Patents/a>/li> li>a hrefpatents.html#publications>Publications/a>/li> li>a hrefpatents.html#short_courses>Short Courses/a>/li> /ul> /ul>/div>div idcaptioned-gallery> figure classslider> figure> img srcimages/slideshow1.png alt> figcaption>Analog mixed-signal / RF IC designp classparagraph>Using state-of-the-art CMOS processes/p>/figcaption> /figure> figure> img srcimages/slideshow2.png alt> figcaption>Assembly of SoCsp classparagraph>Integration of analog mixed signal, memory and processor IPs/p>/figcaption> /figure> figure> img srcimages/slideshow3.png alt> figcaption>High-voltage IC designp classparagraph>Using BCD processes/p>/figcaption> /figure> figure> img srcimages/slideshow4.png alt> figcaption>MMIC designp classparagraph>Using InGaAs pHEMT and GaN HEMT processes/p>/figcaption> /figure> figure> img srcimages/slideshow1.png alt> fig
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